1. Field of Invention
The present invention relates to a method of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing semiconductor devices.
2. Description of Related Art
As semiconductor manufacturing continues to progress, the fabrication of metal-oxide semiconductor (MOS) devices having a smaller line width on a larger chip is rendered possible. With such miniaturization, more powerful functions are incorporated into a single silicon chip at a lower cost. However, as the level of integration increases, dimensions of each device are reduced to 0.18 xcexcm or smaller. A reduction of the channel width of a MOS device often leads to short channel effect and a punch-through of the doped ions in the source/drain regions. Ultimately, the MOS device may lose control.
When short channel effect is important, depletion regions generated at the source/drain regions of a MOS device will affect their mutual connections as well as connection with the channel. Hence, sub-threshold current of the MOS device will increase due to the passage of more electrons. With an increase in sub-threshold current, the MOS device may jump to an xe2x80x9copenxe2x80x9d or a xe2x80x9cclosexe2x80x9d state without a control voltage at the gate of the MOS device and the intended switching action through the application of a gate voltage to a MOS device is lost.
Hot electron effect is another phenomenon that affects the operation of the MOS device as channel length is shortened. When applied voltage across the MOS device remains unchanged, later electric field inside the channel will increase. Hence, some hot electrons having energy higher than the ones at thermal equilibrium may be produced. Through the action of these high-energy hot electrons, a substrate current that may affect normal connectivity of the channel may be generated leading to an electrical breakdown.
One of the most effective means of reducing short channel effect is to form a doped region having a dopant concentration lower than the source/drain region in the original MOS source/drain region close to the channel. This region is referred to as a lightly doped region.
A conventional method of forming a lightly doped drain region in a semiconductor device includes forming a plurality of gate structures inside the memory region and peripheral circuit region of a substrate. Using the gate structure as a mask, a dopant implantation is conducted to form lightly doped regions in the substrate on each side of the gate structure. A silicon nitride layer is formed over the substrate and the silicon nitride layer is etched to form spacers on each sidewall of the gate structure. Thereafter, source/drain regions are formed in the substrate on each side of the gate structure. An N+ source/drain region and a P+ source/drain region are formed in the substrate within the NMOS device region of the peripheral circuit region and on each side of the gate structure within the PMOS device region. A self-aligned contact (SAC) process is conducted to form an inter-dielectric layer over the substrate. A plurality of contact openings that exposes the source/drain regions (including the source/drain regions of the memory cell region and the peripheral circuit region) is formed in the dielectric layer using the spacers as an alignment mask. Finally, conductive material is deposited into the contact openings to form contacts.
In the aforementioned process, if the silicon nitride spacer has considerable thickness (such as 400 xc3x85), short-channel effect and hot electron effect of the device is minimized to an acceptable level. However, as the level of integration of semiconductor devices continues to increase, some problems will appear. As the level of integration increases and the line width of each device shrinks, distance between neighboring gate structures also reduces. Hence, thickness of the silicon nitride spacer must be reduced. Once the spacer thickness is reduced to about 300 xc3x85 or smaller, not only will short-channel effect and hot electron effect re-appear, the spacers will also be over-etched in subsequent self-aligned contact etching process leading to short circuiting between the gate structure and subsequently formed contact.
To counter the problem, a silicon nitride liner layer (having a thickness of about 150 xc3x85) is formed over the substrate before carrying out a self-aligned contact process so that short circuiting between the gate structure and subsequently formed contact due to over-etching can be prevented. Nevertheless, this additional step not only complicates the manufacturing process, but also leads to a reduction in contact area between the contact and the source/drain region and a lowering of device performance. Furthermore, because the process requires two separate etching operations, the substrate may be over-etched leading to a defective lattice structure. On the other hand, if the silicon nitride spacer is too thick, the silicon nitride liner layer formed before the self-aligned process may fill up the gap between neighboring gate structures and hence may affect subsequent manufacturing steps.
Accordingly, one object of the present invention is to provide a method of manufacturing semiconductor devices. By retaining a portion of the silicon nitride layer in the process of forming the lightly doped drain region, the silicon substrate is protected against plasma damage. This residual silicon nitride layer is further capable of attenuating the energy level of both the N+ ions and the P+ ions automatically during an ion implantation so that the device can have a more stable performance.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing semiconductor devices. A gate structure is formed over a substrate. A dopant implantation is carried out to form a lightly doped region in the substrate on each side of the gate structure. An insulation layer is formed over the substrate. A portion of the insulation is later removed so that a portion of the insulation layer is retained over the substrate on each side of the gate structure. A spacer is formed on each sidewall of the gate structure. Another ion implantation is carried out such that the dopants penetrate through the insulation layer on the substrate on each side of the gate structure. Ultimately, a heavily doped region is formed in the substrate outside the spacer-covered region on each side of the gate structure.
In this invention, the insulation layer over the substrate on each side of the gate structures is not entirely removed during the etching operation. Since the insulation layer has a definite thickness, spacers on the sidewalls of the gate structures can have considerable thickness to prevent dopants in subsequently formed source/drain region from diffusing into the lightly doped drain region leading to a deterioration of device properties. Moreover, the insulation layer covers the substrate throughout the etching operation so that damages to the substrate due to over-etching are largely prevented.
Because the spacers have a definite thickness, subsequent self-aligned contact process requires no additional line pad layer to prevent the over-etching of spacers leading to a possible short-circuit between the gate structure and the subsequently formed contact. Hence, this invention not only ensures a sufficient contact area between the contact and the source/drain region, but also reduces the number of processing steps.
In addition, the residual insulation layer over the substrate on each side of the gate structures also prevents possible structural damages to the substrate due to a subsequent dopant (plasma) implantation.
Furthermore, the implanted dopants penetrate through the insulation layer before ending up in the substrate to form a heavily doped region (the source/drain region). Consequently, energy levels of the N+ or P+ ions in the implantation are automatically adjusted to produce a device having a more stable performance.
This invention also provides a second method of forming semiconductor devices. A substrate having a memory cell region and a peripheral circuit region are provided. A plurality of first gate structures is formed on the memory cell region and a plurality of second gate structures is formed on the peripheral circuit region. A lightly doped region is formed in the substrate on each side of the first gate structures and the second gate structures. A first insulation layer is formed over the substrate. A portion of the first insulation layer is removed so that the first insulation layer between neighboring first gate structures and neighboring second gate structures is converted to a second insulation layer. Next, spacers are formed on the sidewalls of the first gate structures and the second gate structures. A first dopant implantation is carried out such that the dopants penetrate through the second insulation layer between neighboring first gate structures to form a first heavily doped region in the substrate on each side of the first gate structures just outside the spacer-covered regions. Similarly, a second dopant implantation is carried out such that the dopants penetrate through the second insulation layer between neighboring second gate structures to form a second heavily doped region in the substrate on each side of the first gate structures just outside the spacer-covered regions. An inter-layer dielectric layer is formed over the substrate. The inter-layer dielectric layer is patterned and the second insulation layer is removed to form a plurality of self-aligned contact openings that expose the first heavily doped regions and the second heavily doped regions. Conductive material is deposited to fill the self-aligned contact openings and form contacts.
In this invention, the first insulation layer over the substrate on each side of the gate structures is not entirely removed during the etching operation. Since the retained second insulation layer has a definite thickness, spacers on the sidewalls of the first and the second gate structures can have considerable thickness to prevent dopants in subsequently formed source/drain region from diffusing into the lightly doped drain region leading to a deterioration of device properties. Moreover, the substrate remains covered throughout the etching of the first insulation layer so that the substrate is prevented from any damage due to over-etching.
Because the spacers have a definite thickness, subsequent self-aligned contact process requires no additional line pad layer to prevent the over-etching of spacers leading to a possible short-circuit between the gate structure and subsequently formed contact. Hence, this invention not only ensures a sufficient contact area between the contact and the source/drain region, but also reduces the number of processing steps.
In addition, the residual second insulation layer over the substrate on each side of the first gate structures and the second gate structures also prevents possible structural damages to the substrate resulting from a subsequently dopant (plasma) implantation.
Furthermore, the implanted dopants penetrate through the second insulation layer before ending up in the substrate to form the heavily doped regions (the source/drain regions). Consequently, energy levels of the N+ or P+ ions in the implantation are automatically adjusted to produce devices having a more stable performance.
Finally, this invention uses fewer and simpler steps so that some production cost is saved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation, of the invention as claimed.